1 of 6 04/26/04 features all-silicon time delay two programmable outputs from a single input produce output-to-output delays between 9ns and 84ns depending on device type programmable via four input pins programmable increments of 3ns to 5ns with a minimum of 9ns and a maximum of 84ns output pulse is a reproduction of input pulse after delay with both leading and trailing edge accuracy standard 16-pin dip or surface mount 16-pin soic auto-insertable low-power cmos design is ttl-compatible pin assignment pin description in - delay line input outa, outb - delay line outputs a0-a3 - parallel program inputs for out1 b0-b3 - parallel program inputs for out2 ea , eb - enable a and b inputs v cc - +5v input gnd - ground description the ds1045 is a programmable silicon delay line having one input and two 4-bit programmable delay outputs. each 4-bit programmable output offers the user 16 possible delay values to select from, starting with a minimum inherent ds1045 delay of 9ns and a maximum achievable delay in the standard ds1045 family of 84ns. the standard ds1045 product line provides the user with three devices having uniform delay increments of 3ns, 4ns, and 5ns, depending on the device. table 1 presents standard device family and delay capability. additionally, custom delay increments are available for special order through dallas semiconductor. the ds1045 is ttl and cmos-compatible and capable of driving ten 74ls-type loads. the output produced by the ds1045 is both rising and falling edge precise. the ds1045 programmable silicon delay line has been designed as a reliable, economic alternative to hybrid programmable delay lines. it is offered in a standard 16-pin auto-insertable dip and a space-saving surface mount 16-pin soic package. ds1045 4-bit dual programmable delay line www.maxim-ic.com in v cc ea a0 a1 a2 a3 gnd v cc eb outb b0 b1 b2 b3 outa 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in v cc 16 1 v cc e a a0 a1 a2 a3 gnd eb outb b0 b1 b2 b3 outa 2 3 4 5 6 7 8 15 14 13 12 11 10 9 ds1045 16-pin dip see mech. drawings section ds1045s 16-pin soic (300-mil) see mech. drawings section
ds1045 2 of 6 parallel programming parallel programming of the ds1045 is accomplished via the set of parallel inputs a0-a3 and b0-b3 as shown in figure 1. parallel input a0-a3 and b0-b3 accept ttl levels and are used to set the delay values of outputs outa and outb, respectively. sixteen possible delay values between the minimum 9ns delay and the maximum delay of the ds1045-x device version can be selected using the parallel programming inputs a0-a3 or b0-b3 (see table 2, ?delay vs. programmed input?). for example, the ds1045-3 outputs outa or outb and can be programmed to produce 16 possible delays between the 9ns (minimum) and the 54ns (maximum) in 3ns increment levels. for applications that do not require frequent reprogramming, the parallel inputs can be set using fixed logic levels, as would be produced by jumpers, dip switches, or ttl levels as produced by computer systems. maximum flexibility in parallel programming can be achieved when inputs are set by computer- generated data. by using the enable input pins for each respective programmed output and observing the input setup (t dse ) and hold time (t dhe ) requirements, data can be latched on an 8-bit bus. if the enable pins, ea and eb , are not used to latch data, they should be set to a logic level 1. after each change in the programmed delay value, a settling time (t edv ) or (t pdv ) is required before the delayed output signal is reliably produced. since the ds1045 is a cmos design, undefined input pins should be connected to well defined logic levels and not left floating. part number table table 1 part number step zero delay max delay time max delay tolerance ds1045-3 9 = 1ns 54ns 2.5ns ds1045-4 9 = 1ns 69ns 3.3ns ds1045-5 9 = 1ns 84ns 4.1ns note: additional delay step times are available from dallas semiconductor by special order. consult factory for availability. block diagram figure 1
ds1045 3 of 6 delay vs. programmed value table 2 part number output delay value ds1045-3 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 ds1045-4 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 ds1045-5 9 14 19 24 29 34 39 44 49 54 59 64 69 74 79 84 program values for each delay value a0 or b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a1 or b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a2 or b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 a3 or b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ds1045 test circuit figure 2 test setup description figure 2 illustrates the hardware configuration used for measuring the timing parameters of the ds1045. the input waveform is produced by a precision pulse generator under software control. time delays are measured by a time interval counter (20 ps resolution) connected to the output. the ds1045 parallel inputs are controlled by an interface to a central computer. all measurements are fully automated with each instrument controlled by the computer over an ieee 488 bus.
ds1045 4 of 6 absolute maximum ratings* voltage on any pin relative to ground -1.0v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature see j-std-020a specification short circuit output current 50ma for 1 second * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol test condition min typ max units notes supply voltage v cc 4.75 5.0 5.25 v 1 input logic 1 v ih 2.2 v cc +0.5 v 1 input logic 0 v il -0.5 0.8 a 1 input leakage i i 0 v i v cc -1.0 +1.0 a active current i cc v cc =5.25v period=1 s 35.0 ma logic 1 output current i oh v cc = 4.75v v oh = 4.0v -1.0 ma logic 0 output current i ol v cc = 4.75v v ol = 0.5v 8 ma ac electrical characteristics (0c to 70c; v cc 5v 5%) parameter symbol min typ max units notes period t period 4 x t wi ns pulse width t wi 100% of output delay ns input to output delay t plh , t phl table 1 ns 2 parallel input change to delay invalid t pdx 0 ns parallel input valid to delay valid t pdv 10 ns enable width t ew 15 ns data setup to enable t dse 10 ns data hold from enable t dhe 0 ns enable to delay invalid t edx 5 ns enable to delay valid t edv 15 ns
ds1045 5 of 6 capacitance (t a = 25c) parameter symbol min typ max units notes input capacitance c in 10 pf test conditions t a =25 c = 3 c v cc = 5.0v = 0.1v input pulse = 3.0v high to 0.0v low = 0.1v input source impedance = 50 ? maximum rise and fall times = 3.0ns max. between 0.6v and 2.4v pulse width = 250ns period = 500ns output load = 74f04 measurement point = 1.5v on inputs and outputs output load capacitance = 15pf note: above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. timing diagram: non-latched parallel mode, e a , eb = v ih timing diagram: latched parallel mode
ds1045 6 of 6 timing diagram: ds1045 inputs to outputs terminology period : the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5v point on the leading edge and the 1.5v point on the trailing edge, or the 1.5v point on the trailing edge and the 1.5v on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t plh (time delay, rising): the elapsed time between the 1.5v point on the leading edge of the input pulse and the 1.5v point on the leading edge of the output pulse. t phl (time delay, falling): the elapsed time between the 1.5v point on the trailing edge of the input pulse and the 1.5v point on the trailing edge of the output pulse. notes: 1. all voltages are referenced to ground. 2. @ v cc = 5v and 25c. delay accurate on both rising and falling edges within tolerances given in table 1.
|
